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<p align="center"></p><p><p> ARM has been doing a good job figuring out its PR strategy as of late. In the span of a couple of years we went from very little outward communication to semi-deep-dives on architecture and a regular cadence of IP disclosures. ARM continues its new trend today with the announcement of its 2015 mid-range CPU IP: the Cortex A17.</p> <p> <span style="-webkit-text-stroke-color: transparent;">As its name implies, the Cortex A17 is a 32-bit ARMv7-A CPU design (64-bit ARMv8 cores belong to the Cortex A50 series - e.g. A53/A57). The best way to think about Cortex A17 is as an evolution of the recently announced Cortex A12, rather than anything to do with the Cortex A15. ARM's Cortex A17 takes the basic 2-wide out-of-order architecture of the Cortex A12 and improves it. Specific details are still light at this point, but I'm told that the front end and execution engine are similar to Cortex A12, with most of the performance/efficiency gains coming from improvements to the memory subsystem. </span></p> <p> The result is a design that is roughly 60% faster than a Cortex A9r4 at a given frequency/process/memory interface, and 40% faster than a Cortex A12 (under the same conditions). Using ARM's own DMIPS/MHz ratings I threw together a little table of relative/estimated performance ratings to help put all of this in perspective:</p> <table align="center" border="0" cellpadding="0" cellspacing="1" width="650"> <tbody> <tr class="tgrey"> <td align="center" colspan="10"> ARM 2014/2015 CPU IP lineup</td> </tr> <tr class="tlblue"> <td width="120"> CPU IP</td> <td align="center" valign="middle" width="85"> Target</td> <td align="center" valign="middle" width="85"> Estimated DMIPS/MHz</td> <td align="center" valign="middle" width="85"> big.LITTLE</td> <td align="center" valign="middle" width="85"> Shipping in Devices/Systems</td> </tr> <tr> <td class="tlgrey"> Cortex A57</td> <td align="center" valign="middle"> High-end mobile/servers</td> <td align="center" valign="middle"> 5*</td> <td align="center" valign="middle"> Yes (w/ A53)</td> <td align="center" valign="middle"> 2015</td> </tr> <tr> <td class="tlgrey"> Cortex A53</td> <td align="center" valign="middle"> Low-end mobile</td> <td align="center" valign="middle"> 2.3</td> <td align="center" valign="middle"> Yes, LITTLE, w/ A57</td> <td align="center" valign="middle"> 2H 2014</td> </tr> <tr> <td class="tlgrey"> Cortex A17</td> <td align="center" valign="middle"> Mid-range mobile</td> <td align="center" valign="middle"> 4.0*</td> <td align="center" valign="middle"> Yes, big, w/ A7</td> <td align="center" valign="middle"> Early 2015</td> </tr> <tr> <td class="tlgrey"> Cortex A15</td> <td align="center" valign="middle"> High-end mobile</td> <td align="center" valign="middle"> 4.0*</td> <td align="center" valign="middle"> Yes, big, w/ A7</td> <td align="center" valign="middle"> Now</td> </tr> <tr> <td class="tlgrey"> Cortex A12</td> <td align="center" valign="middle"> Mid-range mobile</td> <td align="center" valign="middle"> 3.5</td> <td align="center" valign="middle"> No</td> <td align="center" valign="middle"> 2H 2014</td> </tr> <tr> <td class="tlgrey"> Cortex A9</td> <td align="center" valign="middle"> High-end mobile</td> <td align="center" valign="middle"> 2.5</td> <td align="center" valign="middle"> No</td> <td align="center" valign="middle"> Now</td> </tr> <tr> <td class="tlgrey"> Cortex A7</td> <td align="center" valign="middle"> Low-end mobile</td> <td align="center" valign="middle"> 1.9</td> <td align="center" valign="middle"> Yes, LITTLE, w/ A15/A17</td> <td align="center" valign="middle"> Now</td> </tr> </tbody> </table> <p style="text-align: center;"> <em><span style="-webkit-text-stroke-color: transparent;">*Estimate based on ARM's claims</span></em></p> <p> <span style="-webkit-text-stroke-color: transparent;">On a given process node, the Cortex A17 can occupy around 20% more area than a Cortex A9 or a marginal increase over a Cortex A12 design. Running the same workload, ARM expects the Cortex A17 to be 20% more energy efficient than the Cortex A9 (race to sleep), but I'd expect higher peak power consumption from the A17. The Cortex A17 name was deliberately chosen as ARM expects to be able to deliver similar performance to the Cortex A15 </span><span style="-webkit-text-stroke-color: transparent;">(in mobile apps/benchmarks, likely not in absolute performance)</span><span style="-webkit-text-stroke-color: transparent;">, but in a much smaller area and at a lower power. I can't help but wonder if this is what the Cortex A15 should have been from the very beginning, at least for mobile applications.</span></p> <p> ARM expects many early Cortex A17 designs to be built on a 28nm process, with an eventual shift over to 20nm once the cost of that process drops. ARM supplied an interesting slide showcasing the number of transistors $1 will buy you as a function of process node:</p> <p style="text-align: center;"> </p> <p> If you're a fabless semiconductor, it looks like 28nm will be the sweet spot for manufacturing for a little while.</p> <p> Keep in mind that the target market for the Cortex A17, like the Cortex A12, is somewhere in between a device like the Moto G and the latest flagship Galaxy S device from Samsung. </p> <p style="text-align: center;"> </p> <h2> big.LITTLE Support</h2> <p> If you remember back to our analysis of the Cortex A12, the first version of the core didn't support ARM's big.LITTLE (lacking the requisite coherent interface) but a future version was promised with big.LITTLE support. The Cortex A17 is that future version. <span style="-webkit-text-stroke-color: transparent;">In a big.LITTLE configuration, the Cortex A17 will function as the "big" core(s) while the Cortex A7 will serve as the "LITTLE" core(s).</span></p> <p> <span style="-webkit-text-stroke-color: transparent;">Rather than giving the Cortex A12 a new major revision number, ARM improved the design, added big.LITTLE support and called the finished product the Cortex A17. It's an interesting approach to dealing with the fact that ARM can rev/improve a single IP offering many times over the course of its life. In case it isn't already obvious, there won't be a big.LITTLE version of the Cortex A12.</span></p> <p> ARM expects some overlap between Cortex A17 and Cortex A12. If a customer is looking to ship in 2014, Cortex A12 will be the only option for them in the mid-range from ARM. If a customer wants big.LITTLE or they are starting a design now, Cortex A17 is the obvious fit. I expect Cortex A17 will contribute to a relatively short lifespan for Cortex A12 in the grand scheme of things.</p> <p style="text-align: center;"> </p> <p> ARM sees some of the biggest opportunities in addressing the entry level and performance mainstream smartphone markets going forward. With the Cortex A17 aiming at the latter, ARM sees a potential market of around 450 million devices in 2015. The lack of 64-bit support makes ARM's mid-range lineup a little odd, especially considering the Cortex A53 and Cortex A57 will ensure both entry level and high-end smartphones will be 64-bit enabled. While I don't have an issue with a good mid-range device shipping without 64-bit support, I'm not sure how handset and tablet OEMs will feel. With Apple, Intel (and likely Qualcomm), embracing 64-bit-only strategies in mobile, I do wonder just how much success these A12/A17 architectures will have over the long run.</p> <p style="text-align: center;"> </p> <p> ARM tells me we should see the first devices using Cortex A17 CPU cores shipping in early 2015. Cortex A17 IP will be available to ARM customers for implementation by the end of this quarter.</p> </p>
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Source: AnandTech
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